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Verilog和LogiSim中的Tic Tac Toe游戏

...;  wire [1:0] pos_led9;  wire [1:0] who;  // Instantiate the Unit Under Test (UUT)  tic_tac_toe_game uut (   .clock(clock),   .reset(reset),   .play(play),   .pc(pc),   .computer_position(computer_position),   .player_position(player_p...

密码协处理器设计

...c coprocessor Design in VHDL -- VHDL code for Combinational Logic unit of the coprocessor entity structural_VHDL is port ( A_BUS: in std_logic_vector(15 downto 0);    B_BUS: in std_logic_vector(15 downto 0);    CTRL: in std_logic_vector(3 downto 0);    RESULT: out...

打地鼠游戏的视觉识别实现

...p; //把合格的图片保存起来     cout << "The image is good" << endl;  }  else  {   cout << "The image is bad please try again" << endl;  }  //  cout << "Press any key to co...

OpenDDS手册中文版

...A Feature Enabled Or Disabled. PAGEREF _Toc522634569 \h 231.3.2 Disabling The Building Of Built-In Topic Support PAGEREF _Toc522634570 \h 241.3.3 Disabling The Building Of Compliance Profile Features. PAGEREF _Toc522634571 \h 241.3.3.1 内容订阅配置文件(Content-Subscription Profile)....

linux驱动程序项目

...p;*  * Allows to provide arch independent atomic definitions without the need to  * edit all arch specific atomic.h files.  */ #include <asm/types.h> /*  * Suppport for atomic_long_t  *  * Casts for parameters are avoided for existing atomic functions in o...

在JAVA中下载网站复印机项目

...mitSpeed;         //Maximum throughput of the transfer     public static int nbBytesPerS;         private static boolean firstLaunch = false;    public Configuration(){       ...

notepad

...open() { QString fileName = QFileDialog::getOpenFileName(this, "Open the file"); QFile file(fileName); currentFile = fileName; if (!file.open(QIODevice::ReadOnly | QFile::Text)) { QMessageBox::warning(this, "Warning", "Cannot open file: " + file.errorString()); ...

电力系统暂态分析

... fprintf(' iterations.\n\n')   fprintf('Press Enter to terminate the iterations and print the results \n')   converge = 0; pause, else, end   endif converge ~= 1   tech= ('                      ITERATIVE S...

使用WLS进行电力系统状态估计

...Ri = diag(zdata(:,6)); % Measurement Error..V = ones(nbus,1); % Initialize the bus voltages..del = zeros(nbus,1); % Initialize the bus angles..E = [del(2:end); V];   % State Vector..G = real(ybus);B = imag(ybus);vi = find(type == 1); % Index of voltage magnitude measurements..ppi = find(ty...

Verilog中的流水线MIPS处理器(第2部分)

...dsub(Out,cout,a,b,cin,select); input a,b,cin,select; output Out,cout; // the result and carry out not #(50) not1(notb,b); mux21 mux1(b1,b,notb,select); adder adder1(Out,cout,a,b1,cin); endmodule `timescale 1 ps / 100 fs module adder(sum,cout,a,b,cin); input   a,b,cin; output&nbsp...

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