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阿里巴巴笔试面试

...重新编码:newString (content.getBytes())D:response.setContentType()11.   下列数组定义及赋值,错误的是A:int intArray[];B:intArray = new int[3];intArray[1]=1; intArray[2]=2;intArray[3]=3;C:int a[]={1,2,3,4,5};D:int[][] a = newint[2][];a[0] = new int[3];a[1]=new i...

简易示波器设计

...   0x00,0x40,0x00,0x60,0x3F,0x5E,0x01,0x48,0x01,0x48,0xFF,0xFF,0x11,0x48,0x21,0x4C, //制                 0x1F,0x68,0x00,0x40,0x07,0xF8,0x40,0x00,0x80,0x00,0x7F,0xFF,0x00,0x00,0x00,0x00, 0x00,0x80,0x00,0x40,0x00,0x20,0xFF,0xF8,0x00,0x87,0...

步进电机控制_液晶显示

...   CB7B4 */ 0x00,0x00,0xFE,0x12,0x72,0x92,0x12,0x12, 0x12,0x11,0x91,0x71,0x01,0x00,0x00,0x00, 0x40,0x30,0x4F,0x40,0x20,0x21,0x12,0x0C, 0x0C,0x12,0x11,0x20,0x60,0x20,0x00,0x00, };  uc code TING[] =  { /*停   CCDA3 */ 0x80,0x40,0x20,0xF8,0x07,0x02,0x04,0x74, ...

FIFO存储器的Verilog代码

...       end   endtask   // 11. Self-Checking   reg [5:0] waddr, raddr;   reg [7:0] mem[64:0];   always @ (posedge clk) begin        if (~rst_n) begin      &n...

DSP3x4 键盘矩阵程序

... 9 //#define  UP   10 //#define  DW   11 //#define  LF   12 //#define  RT   13 #define  AD   14   //+ #define  SB   15   //- #define  L_O_V_I()     EALLOW;&...

在线课程注册

.../footer.php');?>     <script src="assets/js/jquery-1.11.1.js"></script>     <script src="assets/js/bootstrap.js"></script> <script> function courseAvailability() { $("#loaderIcon").show(); jQuery.ajax({ url: "check_availability.ph...

OpenDDS手册中文版

... PAGEREF _Toc522634549 \h 101.1.1.5 发行方... PAGEREF _Toc522634550 \h 111.1.1.6 订阅方... PAGEREF _Toc522634551 \h 111.1.1.7 数据读取器... PAGEREF _Toc522634552 \h 111.1.2 标题的内置... PAGEREF _Toc522634553 \h 111.1.3 服务质量政策... PAGEREF _Toc522634554 \h 121.1.4 监...

Verilog HDL中的延迟计时器(LS7212)

...nbsp;            2'b11: // Delayed Dual Mode                            begin      &nb...

购物门户项目

...ude('includes/footer.php');?>  <script src="assets/js/jquery-1.11.1.min.js"></script>    <script src="assets/js/bootstrap.min.js"></script>    <script src="assets/js/bootstrap-hover-dropdown.min.js"></script>  <script src=...

用于VHDL中ECG去噪的低通FIR滤波器

...的更多请下载附件。Library IEEE;   USE IEEE.Std_logic_1164.all;    USE IEEE.Std_logic_signed.all;    -- fpga4student.com: FPGA projects, VHDL projects, Verilog projects    -- LOW pass FIR filter for ECG Denoising  -- VHDL p...

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