为您找到约 41 条结果，搜索耗时：0.0084秒

1Khz 220V方波可调频调压TL494开关电源设计

使用电力二极管整流桥对输入的220V/50Hz正弦波进行全桥整流，整流后使用电容进行滤波，滤波以后电压曲线近似直流，再输入单相半桥逆变桥，使用电力MOSFET进行半桥逆变，通过控制触发信号控制MOS管的开关从而实现对电压方向...

基于FPGA多通道采样系统设计论文资料

...，为此模拟信号选用音频信号。由于音频信号的频率是20Hz-20KHz,这样就对AD转换的速率有很高的要求.因为FPGA的功能很强大，所以我们把系统的许多功能都集成到FPGA器件中，例如AD通道选择部分，串并输出控制模块，这样使得整个...

电力系统暂态仿真

...分别进行了暂态仿真，有阻尼仿真 XL_km=0.367; % ohm/km at 60 Hz RL_km= 0.1*XL_km; % Resistance in ohm/km KV_LL= 345; MVA_Base=100; % common 3-phase base Z_Base=KV_LL^2/MVA_Base; % common base % YBUS Creation Z13_ohm=(RL_km+j*XL_km)*200; B13_Micro_Mho=4.5*200; % Line 1-3 is 200...

matlab和powerworld潮流计算

... kVLL=345; MVA3Ph=100; Zbase=kVLL^2/MVA3Ph; XL_km=0.376; % ohm/km at 60 Hz RL_km= 0.037; B_km=4.5; % B in micro-mho/km %---------Line Susceptances--------% B13_Micro_Mho=4.5*200; %200 km long B12_Micro_Mho=4.5*150; %150 km long B23_Micro_Mho=4.5*150; %150 km long %---------Line impedances--...

单相桥式可控整流电路.

...峰值（peak amplitude, V）=141.4V(有效值为100V)，频率(Frequency, Hz)＝50脉冲发生器1(ug1)：周期（period, s）＝0.02 ；脉冲宽度（pulse width, % of  period）＝2;滞后相位（phase delay, s）=0; (α=0˚)脉冲发生器2(ug2)：周期（period, s）＝0.02 ；脉冲...

电力系统的稳定性和控制

...(j*deg2rad*(EB_angle));      % polar notation%% A 555MVA, 60Hz turbine generator has the following parameters:% GIVEN SPECIFICAITON:S = 555e6;      %[VA] total power basef0 = 60;         %[Hz] frequencyXd=1.81;    % note that in PU sys...

ADV7842—adc芯片linux驱动

...: Positive or negative polarities * @pixelclock: Pixel clock in HZ. Ex. 74.25MHz->74250000 * @hfrontporch:Horizontal front porch in pixels * @hsync: Horizontal Sync length in pixels * @hbackporch: Horizontal back porch in pixels * @vfrontporch:Vertical front porch in line...

基于VHDL的可变占空比PWM发生器

...; entity PWM_Generator is port (    clk: in std_logic; -- 100MHz clock input    DUTY_INCREASE: in std_logic; -- button to increase duty cycle by 10%    DUTY_DECREASE: in std_logic; -- button to decrease duty cycle by 10%    PWM_OUT: out std_logic -- PWM...

传感器演示

...Log(@"手机没有此功能，换肾吧"); } //更新速率是100Hz self.motionManager.deviceMotionUpdateInterval = 0.1; //开始更新采集数据 //需要时采集数据 //[motionManager startDeviceMotionUpdates]; //实时获取数据 [self.motionManager sta...

FPGA上数字时钟的VHDL代码

...mal operation, this input pin should be 0*/  input clk,  /* A 10Hz input clock. This should be used to generate each real-time second*/  input [1:0] H_in1, /*A 2-bit input used to set the most significant hour digit of the clock (if LD_time=1),or the most significant hour digit of t...