-
-
...nbsp; );
end ALU;
architecture Behavioral of ALU is
signal ALU_Result : std_logic_vector (7 downto 0);
signal tmp: std_logic_vector (8 downto 0);
begin
process(A,B,ALU_Sel)
begin
case(ALU_Sel) is
when "0000" => -- Addition
ALU_R...
-
-
... ALU;
architecture Behavioral of ALU is
signal ALU_Result:std_logic_vector(7 downto 0);
signal ALU_ADD: std_logic_vector(8 downto 0);
signal C,Z,V,N,add_ov,sub_ov: std_logic;
begin
process(ALU_Sel,A,B)
...
-
-
...nbsp; output[15:0] pc_out, alu_result
//,reg3,reg4
);
reg[1...
