...ral_VHDL is
port ( A_BUS: in std_logic_vector(15 downto 0);
B_BUS: in std_logic_vector(15 downto 0);
CTRL: in std_logic_vector(3 downto 0);
RESULT: out std_logic_vector(15 downto 0)
);
end structural_VHDL;
architecture Behavioral of structural_VHD...
