-
-
... std_logic
);
end RisingEdge_DFlipFlop;
architecture Behavioral of RisingEdge_DFlipFlop is
begin
process(Clk)
begin
if(rising_edge(Clk)) then
Q <= D;
end if; &n...
-
-
... -- PWM signal out with frequency of 10MHz
);
end PWM_Generator;
architecture Behavioral of PWM_Generator is
-- D-Flip-Flop for debouncing module
component DFF_Debounce
Port (
CLK : in std_logic;
en : in std_logic;
D : in std_logic;
Q ...
-
-
... 0) -- output 4-bit counter
);
end UP_COUNTER;
architecture Behavioral of UP_COUNTER is
signal counter_up: std_logic_vector(3 downto 0);
begin
-- up counter
process(clk,reset)
begin
if(rising_edge(clk)) then
if(reset='1') then
...
-
-
...我们的服务器是否实际运行在AMD CPU：
# lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
...
Thread(s) per core: 1
Core(s) per socket: 32
Socket(s): 1
NUMA node(s): 4
Vendor ID: Aut...
-
-
...utput: out std_logic -- Output = 0 when A = B
);
end comparator;
architecture Behavioral of comparator is
signal AB: std_logic_vector(7 downto 0); -- temporary variables
signal Result: std_logic;
begin
AB(0) <= (not A(0)) xnor (not B(0)); &nb...
-
-
...UTOUT: out std_logic_vector(7 downto 0)
);
end non_linear_lookup;
architecture Behavioral of non_linear_lookup is
signal MSN_in,LSN_in,MSN_out,LSN_out: std_logic_vector(3 downto 0);
begin
MSN_in <= LUTIN(7 downto 4);
LSN_in <= LUTIN(3 downto 0);
SBOX_1: process(MSN_in) begin
cas...
-
-
...nbsp; -- 16-bit data output of the 16-bit ALU
);
end ALU;
architecture Behavioral of ALU is
-- N-bit Adder in Verilog
component N_bit_adder is
generic (
N: integer:=32
);
port( input1: in std_logic_vector(N-1 downto 0);
input2: in std_l...
-
-
... ;-- output data
end FIR_RI;
architecture behaivioral of FIR_RI is
-- N bit Register
component N_bit_Reg
generic (
input_width  ...
-
-
...ESULT: out std_logic_vector(15 downto 0)
);
end structural_VHDL;
architecture Behavioral of structural_VHDL is
component non_linear_lookup is
port ( LUTIN: in std_logic_vector(7 downto 0);
LUTOUT: out std_logic_vector(7 downto 0)
);
end component non_linear_lo...
-
-
...bsp; -- Carryout flag
);
end ALU;
architecture Behavioral of ALU is
signal ALU_Result : std_logic_vector (7 downto 0);
signal tmp: std_logic_vector (8 downto 0);
begin
process(A,B,ALU_Sel)
begin
case(ALU_Sel) is
when "0...
