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此项目是verilog编译器指令；附件详细的介绍了属于IEEE-1364的一些指令，有include指令、define指令、undef指令、ifdef指令。使用ifdef指令示例如下：使用ifdef指令示例
1 module ifdef ();
2
3 initial begin
4 `ifdef FIRST
&n...
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...请下载附件。-- fpga4student.com
-- FPGA projects, VHDL projects, Verilog projects
-- VHDL code for full adder
-- Structural code for full adder
library ieee;
use ieee.std_logic_1164.all;
entity Full_Adder_Structural_VHDL is
port(
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// This is my second Verilog Design
// Design Name : first_counter
// File Name : first_counter.v
// Function : This is a 4 bit up-counter with
// Synchronous active high reset and
// with active high enable signal
//-----------------------...
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...如想了解得更多请下载附件。-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for matrix multiplcation
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ...
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...ll;
-- fpga4student.com: FPGA projects, VHDL projects, Verilog projects
-- LOW pass FIR filter for ECG Denoising
-- VHDL project: VHDL code for FIR filter
entity FIR_RI is -- VHDL projects
generic (
&...
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...y IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for Shifter
entity shifter is
generic ( N: integer:=16
);
Port ( SHIFTINPUT : in STD_LOGIC_VECTOR(N-1 downto 0);
&n...
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...；如想了解更多请下载附件。-- fpga4student.com: FPGA Projects, Verilog projects, VHDL projects
-- VHDL code for PWM Generator
-- Two de-bounced push-buttons
-- One: increase duty cycle by 10%
-- Another: Decrease duty cycle by 10%
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE I...
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...USE ieee.std_logic_unsigned.all;
--fpga4student.com FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for 8-bit Microcontroller
-- Submodule VHDL code: ALU
entity ALU is
port (
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...EEE.STD_LOGIC_1164.ALL;
-- fpga4student.com FPGA projects, VHDL projects, Verilog projects
-- VHDL project: VHDL code for ring counter
-- VHDL code for DFF
entity DFF is
port(
Q : out std_logic; -- Data output
&nb...
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...y IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL implementation of Lookup Table
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-- Non-linear Lookup Table Implementation in VHDL--
--------------------------------...
