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带测试平台的计数器的VHDL代码

...ogic_vector(3 downto 0); begin -- up counter process(clk,reset) begin if(rising_edge(clk)) then     if(reset='1') then          counter_up <= x"0";     else         counter_up <= c...

Verilog HDL中的延迟计时器(LS7212)

...nbsp; reset_det2 <= reset_det1;   end   // Identify the zero to one transitions on trigger signal   assign trigger_rising = trigger_sync_1 & (~trigger_sync_2);    assign trigger_falling = trigger_sync_2 & (~trigger_sync_1);   ...

双单片机串口例子

...e=2400 TL1=0xf3; ET1=1; TR1=1; EA=1; ES=1; while(1) { if (key_in != key_port) { key_in = key_port; SBUF=key_in; } } } void get_disp (void) interrupt 4 using 0 { if (RI) //如果是串口输入引起中断 { dis_port = SBUF; RI=0; } ...

步进电机控制_液晶显示

...nbsp; disrow(uc page,uc col,uc *temp)  {    uc i;   if(col<64)                                         // 左半平面   {      L=1;R=0; wcode(LCDPAGE...

Infiniband 网卡驱动安装的坑

... next; for (n = from; n < to; n = next) { next = MKDEV(MAJOR(n)+1, 0); if (next > to) next = to; cd = __register_chrdev_region(MAJOR(n), MINOR(n), next - n, name); if (IS_ERR(cd)) goto fail; } return 0;fail: to = n; for (n = from; n < to; n = next) { next = MKDEV(MAJOR(n)+1, 0); kfree(__un...

机器人视觉模式识别

...p;CvPoint2D32f center;  CvPoint pt1, pt2;  CvRect rect;  if (argc >= 2)   src_img = cvLoadImage (argv[1], CV_LOAD_IMAGE_ANYDEPTH | CV_LOAD_IMAGE_ANYCOLOR);  if (src_img == 0)   return -1;  rect.x = (int) (src_img->width * 0.25);  rect.y...

温度计设计

...   dat>>=1;   DQ = 1; // 给脉冲信号   if(DQ)   dat|=0x80;   delay_18B20(4); }   return(dat); } //写一个字节   WriteOneChar(unsigned char dat) {  unsigned char i=0;  for (i=8; i>0; i--)  {   DQ...

AD_DS1621与12864液晶

...P2;//读状态标志寄存器 _nop;     E=Low;     if((busy&0x90)==0)//检测BF和RES位,两者都为零时表示可进行写入     break;   };  } /*********************************          写指令 ******************...

实验室的仿真测试代码库

...ind);Rs_compRx2(k,i,:)=Rs_comp2(get_ind);endflag_save=1;    if flag_save==1        if exist('DataContainer_0603.mat')==0           save('DataContainer_0604_V2','containerRx1','containerRx2','Absmotion...

算术逻辑单元(ALU)的VHDL代码

...A)) / to_integer(unsigned(B)),8)) ;   when "0100" => -- Logical shift left    ALU_Result <= std_logic_vector(unsigned(A) sll N);   when "0101" => -- Logical shift right    ALU_Result <= std_logic_vector(unsigned(A) srl N);   when "0110" => --&nb...

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