-
-
...载建模为电压相关和独立的负载。本文使用的测试系统是IEEE 9总线和68总线系统,以及德克萨斯州的2007总线综合电源系统。不同类型的干扰适用于系统,包括发电机侧干扰和网络侧干扰。结果证明了该软件包对研究人员和学生的...
-
-
...境中建模,并分析了各种条件下的系统性能。最后,基于IEEE 1547标准对仿真结果进行了评估,并证明了所提出系统的有效性
-
-
...VHDL code for 16-bit ALU
-- Top level VHDL code for 16-bit ALU
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- 16-bit ALU
entity ALU is
port (
ABUS: in std_logic_vector(15 downto 0); -- ABUS data input of the 16-bit ALU
BBUS: in std_logic_vector(15 downto 0);...
-
-
...t opendssdirect as dss
dss.run_command('Redirect ../../tests/data/13Bus/IEEE13Nodeckt.dss')
dss.Circuit.AllBusNames()
dss.run_command(
"New Storage.{bus_name} Bus1={bus_name} phases=1 kV=2.2 kWRated={rating} kWhRated={kwh_rating} kWhStored={initial_state} %IdlingkW=0 %reserve=0 %EffCha...
-
-
...合逻辑单元的VHDL代码;如想了解更多请下载附件。library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: Cryptographic coprocessor Design in VHDL
-- VHDL code for Combinational Logic unit of the coprocessor...
-
-
...FIR滤波器的VHDL代码;如想了解的更多请下载附件。Library IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.Std_logic_signed.all;
-- fpga4student.com: FPGA projects, VHDL projects, Verilog projects
-- LOW pass FIR f...
-
-
...stermann: "On the Optimization of the Load of Electric Vehicles",04: 2011, IEEE General Meeting 2011; Dirk Westermann, Michael Agsten, Steffen Schlegel, Mike Ifland: "Utilizing Battery Electric Vehicles and Plug-In Hybrids for Smart Grid Operation Techniques",03: 2011, Beitrag in der Automatisierung...
-
-
这是用opendss仿真的 34节点算例, IEEE34节点算例,部分参数如下: 阻抗参数如下; --------- Z & B Matrices Before Changes --------- Z (R +jX) in ohms per mile 1.3368 1.3343  ...
-
-
...nbus = 14; % IEEE-14, IEEE-30, IEEE-57..Y = ybusppg(nbus); % Calling ybusppg.m to get Y-Bus Matrix..busd = busdatas(nbus); % Calling busdatas..BMva = 100; &n...
-
-
...p; = DSSCircuit.Loads;
Projpath = [pwd,'\IEEE_519.dss'];
DSSText.Command='Clear';
DSSText.Command=['Compile "',Projpath,'"'];
%Gets the names and nominal powers (P) for each load
%You can improev ...