应用介绍

此项目是介绍了延迟控制、边沿触发的事件控制、电平触发的时间控制、赋值语句中的内部时间控制、使用连续赋值语句为组合逻辑电路建模。本人是展示了延时控制的代码和输出结果；其他的代码和输出结果在附件。

延迟控制：
 1 module clk_gen ();
  2 
  3 reg clk, reset; 
  4 
  5 initial begin
  6   $monitor ("TIME = %g RESET = %b CLOCK = %b", $time, reset, clk);
  7   clk = 0; 
  8   reset = 0; 
  9    #2  reset = 1; 
 10    #5  reset = 0; 
 11    #10  $finish;
 12 end 
 13 
 14 always 
 15    #1  clk =  ! clk;
 16 
 17 endmodule

输出：

TIME = 0  RESET = 0 CLOCK = 0

 TIME = 1  RESET = 0 CLOCK = 1

 TIME = 2  RESET = 1 CLOCK = 0

 TIME = 3  RESET = 1 CLOCK = 1

 TIME = 4  RESET = 1 CLOCK = 0

 TIME = 5  RESET = 1 CLOCK = 1

 TIME = 6  RESET = 1 CLOCK = 0

 TIME = 7  RESET = 0 CLOCK = 1

 TIME = 8  RESET = 0 CLOCK = 0

 TIME = 9  RESET = 0 CLOCK = 1

 TIME = 10 RESET = 0 CLOCK = 0

 TIME = 11 RESET = 0 CLOCK = 1

 TIME = 12 RESET = 0 CLOCK = 0

 TIME = 13 RESET = 0 CLOCK = 1

 TIME = 14 RESET = 0 CLOCK = 0

 TIME = 15 RESET = 0 CLOCK = 1

 TIME = 16 RESET = 0 CLOCK = 0