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4x4乘法器的Verilog代码

...展示了乘法器的Verilog代码:`timescale 1ns / 1ps // fpga4student.com FPGA projects, Verilog projects, VHDL projects // multiplier 4x4 using Shift/Add Algorithm and 2-phase clocking system // Verilog project: Verilog code for multiplier module mult_4x4(      &nb...

全加法器的VHDL代码

...器的VHDL代码;如想了解的更多请下载附件。-- fpga4student.com -- FPGA projects, VHDL projects, Verilog projects -- VHDL code for full adder -- Structural code for full adder  library ieee;  use ieee.std_logic_1164.all;   entity Full_Adder_Structural_VH...

蓝桥杯嵌入式源代码

...新至心得总结5.可用于学习、参考。转载联系2583518067@qq.com6.如果对你有用,希望能动动小手点个Star,让我有动力持续更新.#软件架构说明 硬件平台:国信长天CT117E 主控芯片:STM32F103RBT6 操作系统:Windows 11 开发环...

STM32学习例子

...e_USART_DMAExample_USB_KeyboardExample_USB_Mass_StorageExample_USB_Virtual_Com_PortExample_WatchdogExample_WG12864A

git 往gitlab上传文件

...it库cd delProcess///添加git库文件git add .//提交文件到git库git commit -m *  git remote add origin http://47.92.171.77/yhood/delProcess.git//上传到远程库git push origin main  或者git push origin master(根据实际情况)引用链接:添加文件夹时//进入gi...

得分系统

...bsp;       "Read more about it at https://getcomposer.org/doc/01-basic-usage.md#composer-lock-the-lock-file",         "This file is @generated automatically"     ],     "hash": "88fd8474bb5c6ee671a6aee3...

接收指纹识别

...not already there }在Module中build.gradle中配置 :dependencies { compile 'com.zwh:RxFingerPrinter:1.2.1' }创建一个 RxFingerPrinter实例 :RxFingerPrinter rxFingerPrinter = new RxFingerPrinter(this); // where this is an Activity instance在需要开启指纹识别的地方执行begin...

使用VHDL的矩阵乘法设计

...VHDL顶级代码;如想了解得更多请下载附件。-- fpga4student.com FPGA projects, Verilog projects, VHDL projects  -- VHDL project: VHDL code for matrix multiplcation  library ieee;    use ieee.std_logic_1164.all;    use ieee.numeric_std.all;...

openDSS开源工具箱Grid pv

...提供的开放源码软件,是一种配电系统仿真器。MATLAB通过COM接口提供前端用户界面来控制OpenDSS。OpenDSS基于命令,可视化能力有限。通过将OpenDSS的控制引入MATLAB,在增加MATLAB循环、高级分析和可视化能力的同时,充分利用了OpenDS...

FPGA上的Verilog车牌识别

...Verilog代码;如想了解得更详细请下载附件。// fpga4student.com FPGA projects, Verilog projects, VHDL projects // Verilog project: License Plate Recognition in Verilog and Matlab // Top level module for testing the license plate recognition system module Test_top(input clk // 33MH...

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