FIFO存储器的VHDL代码
此项目是FIFO存储器的VHDL代码。FIFO具有16个8位数据宽度级和五个状态信号，包括上溢，下溢，空，满和阈值。 通过在Xilinx ISIM上进行混合语言仿真，使用相同的Verilog测试平台代码验证FIFO存储器的VHDL代码。通过观察可以很容易地看到如何将数据写入FIFO以及如何从FIFO读取数据。 值得注意的是，状态信号（例如上溢，下溢，空，满）对于确定FIFO的正确性至关重要。
应用介绍
此项目是FIFO存储器的VHDL代码。
FIFO具有16个8位数据宽度级和五个状态信号，包括上溢，下溢，空，满和阈值。 通过在Xilinx ISIM上进行混合语言仿真，使用相同的Verilog测试平台代码验证FIFO存储器的VHDL代码。
通过观察可以很容易地看到如何将数据写入FIFO以及如何从FIFO读取数据。 值得注意的是，状态信号（例如上溢，下溢，空，满）对于确定FIFO的正确性至关重要。
附件文件包括：FIFO的VHDL代码、运行模拟后正确的结果。
本人在下方展示了运行模拟后正确的结果；如想了解的更多请下载附件。
TIME = 110, data_out = 1, mem = 1
TIME = 120, wr = 1, rd = 0, data_in = 02
TIME = 130, data_out = 1, mem = 1
TIME = 140, wr = 0, rd = 0, data_in = 02
TIME = 150, data_out = 1, mem = 1
TIME = 170, data_out = 1, mem = 1
TIME = 190, data_out = 1, mem = 1
TIME = 190, wr = 1, rd = 0, data_in = 03
TIME = 210, data_out = 1, mem = 1
TIME = 210, wr = 0, rd = 0, data_in = 03
TIME = 230, data_out = 1, mem = 1
TIME = 250, data_out = 1, mem = 1
TIME = 260, wr = 1, rd = 0, data_in = 04
TIME = 270, data_out = 1, mem = 1
TIME = 280, wr = 0, rd = 0, data_in = 04
TIME = 290, data_out = 1, mem = 1
TIME = 310, data_out = 1, mem = 1
TIME = 330, data_out = 1, mem = 1
TIME = 330, wr = 1, rd = 0, data_in = 05
TIME = 350, data_out = 1, mem = 1
TIME = 350, wr = 0, rd = 0, data_in = 05
TIME = 370, data_out = 1, mem = 1
TIME = 390, data_out = 1, mem = 1
TIME = 400, wr = 1, rd = 0, data_in = 06
TIME = 410, data_out = 1, mem = 1
TIME = 420, wr = 0, rd = 0, data_in = 06
TIME = 430, data_out = 1, mem = 1
TIME = 450, data_out = 1, mem = 1
TIME = 470, data_out = 1, mem = 1
TIME = 470, wr = 1, rd = 0, data_in = 07
TIME = 490, data_out = 1, mem = 1
TIME = 490, wr = 0, rd = 0, data_in = 07
TIME = 510, data_out = 1, mem = 1
TIME = 530, data_out = 1, mem = 1
TIME = 540, wr = 1, rd = 0, data_in = 08
TIME = 550, data_out = 1, mem = 1
TIME = 560, wr = 0, rd = 0, data_in = 08
TIME = 570, data_out = 1, mem = 1
TIME = 590, data_out = 1, mem = 1
TIME = 610, data_out = 1, mem = 1
TIME = 610, wr = 1, rd = 0, data_in = 09
TIME = 630, data_out = 1, mem = 1
TIME = 630, wr = 0, rd = 0, data_in = 09
TIME = 650, data_out = 1, mem = 1
TIME = 670, data_out = 1, mem = 1
TIME = 680, wr = 1, rd = 0, data_in = 0a
TIME = 690, data_out = 1, mem = 1
TIME = 700, wr = 0, rd = 0, data_in = 0a
TIME = 710, data_out = 1, mem = 1
TIME = 730, data_out = 1, mem = 1
TIME = 750, data_out = 1, mem = 1
TIME = 750, wr = 1, rd = 0, data_in = 0b
TIME = 770, data_out = 1, mem = 1
TIME = 770, wr = 0, rd = 0, data_in = 0b
TIME = 790, data_out = 1, mem = 1
TIME = 810, data_out = 1, mem = 1
TIME = 820, wr = 1, rd = 0, data_in = 0c
TIME = 830, data_out = 1, mem = 1
TIME = 840, wr = 0, rd = 0, data_in = 0c
TIME = 850, data_out = 1, mem = 1
TIME = 870, data_out = 1, mem = 1
TIME = 890, data_out = 1, mem = 1
TIME = 890, wr = 1, rd = 0, data_in = 0d
TIME = 910, data_out = 1, mem = 1
TIME = 910, wr = 0, rd = 0, data_in = 0d
TIME = 930, data_out = 1, mem = 1
TIME = 950, data_out = 1, mem = 1
TIME = 960, wr = 1, rd = 0, data_in = 0e
TIME = 970, data_out = 1, mem = 1
TIME = 980, wr = 0, rd = 0, data_in = 0e
TIME = 990, data_out = 1, mem = 1
TIME = 1010, data_out = 1, mem = 1
TIME = 1030, data_out = 1, mem = 1
TIME = 1030, wr = 1, rd = 0, data_in = 0f
TIME = 1050, data_out = 1, mem = 1
TIME = 1050, wr = 0, rd = 0, data_in = 0f
TIME = 1070, data_out = 1, mem = 1
TIME = 1090, data_out = 1, mem = 1
TIME = 1100, wr = 1, rd = 0, data_in = 10
TIME = 1110, data_out = 1, mem = 1
TIME = 1120, wr = 0, rd = 0, data_in = 10
TIME = 1130, data_out = 1, mem = 1
TIME = 1150, data_out = 1, mem = 1
TIME = 1170, data_out = 1, mem = 1
TIME = 1170, wr = 1, rd = 0, data_in = 11
TIME = 1190, data_out = 1, mem = 1
TIME = 1190, wr = 0, rd = 0, data_in = 11
TIME = 1210, data_out = 1, mem = 1
TIME = 1220, wr = 0, rd = 1, data_in = 11
TIME = 1230, data_out = 1, mem = 1
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1240, wr = 0, rd = 0, data_in = 11
TIME = 1250, data_out = 2, mem = 2
TIME = 1260, wr = 0, rd = 1, data_in = 11
TIME = 1270, data_out = 2, mem = 2
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1280, wr = 0, rd = 0, data_in = 11
TIME = 1290, data_out = 3, mem = 3
TIME = 1300, wr = 0, rd = 1, data_in = 11
TIME = 1310, data_out = 3, mem = 3
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1320, wr = 0, rd = 0, data_in = 11
TIME = 1330, data_out = 4, mem = 4
TIME = 1340, wr = 0, rd = 1, data_in = 11
TIME = 1350, data_out = 4, mem = 4
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1360, wr = 0, rd = 0, data_in = 11
TIME = 1370, data_out = 5, mem = 5
TIME = 1380, wr = 0, rd = 1, data_in = 11
TIME = 1390, data_out = 5, mem = 5
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1400, wr = 0, rd = 0, data_in = 11
TIME = 1410, data_out = 6, mem = 6
TIME = 1420, wr = 0, rd = 1, data_in = 11
TIME = 1430, data_out = 6, mem = 6
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1440, wr = 0, rd = 0, data_in = 11
TIME = 1450, data_out = 7, mem = 7
TIME = 1460, wr = 0, rd = 1, data_in = 11
TIME = 1470, data_out = 7, mem = 7
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1480, wr = 0, rd = 0, data_in = 11
TIME = 1490, data_out = 8, mem = 8
TIME = 1500, wr = 0, rd = 1, data_in = 11
TIME = 1510, data_out = 8, mem = 8
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1520, wr = 0, rd = 0, data_in = 11
TIME = 1530, data_out = 9, mem = 9
TIME = 1540, wr = 0, rd = 1, data_in = 11
TIME = 1550, data_out = 9, mem = 9
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1560, wr = 0, rd = 0, data_in = 11
TIME = 1570, data_out = 10, mem = 10
TIME = 1580, wr = 0, rd = 1, data_in = 11
TIME = 1590, data_out = 10, mem = 10
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1600, wr = 0, rd = 0, data_in = 11
TIME = 1610, data_out = 11, mem = 11
TIME = 1620, wr = 0, rd = 1, data_in = 11
TIME = 1630, data_out = 11, mem = 11
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1640, wr = 0, rd = 0, data_in = 11
TIME = 1650, data_out = 12, mem = 12
TIME = 1660, wr = 0, rd = 1, data_in = 11
TIME = 1670, data_out = 12, mem = 12
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1680, wr = 0, rd = 0, data_in = 11
TIME = 1690, data_out = 13, mem = 13
TIME = 1700, wr = 0, rd = 1, data_in = 11
TIME = 1710, data_out = 13, mem = 13
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1720, wr = 0, rd = 0, data_in = 11
TIME = 1730, data_out = 14, mem = 14
TIME = 1740, wr = 0, rd = 1, data_in = 11
TIME = 1750, data_out = 14, mem = 14
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1760, wr = 0, rd = 0, data_in = 11
TIME = 1770, data_out = 15, mem = 15
TIME = 1780, wr = 0, rd = 1, data_in = 11
TIME = 1790, data_out = 15, mem = 15
PASS ------ PASS ---------- PASS -------------- PASS
TIME = 1800, wr = 0, rd = 0, data_in = 11
TIME = 1810, data_out = 16, mem = 16
TIME = 1820, wr = 0, rd = 1, data_in = 11
TIME = 1830, data_out = 16, mem = 16
PASS ------ PASS ---------- PASS -------------- PASS
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文件列表(部分)
| 名称 | 大小 | 修改日期 |
|---|---|---|
| FIFO存储器的VHDL代码(附件).txt | 2.06 KB | 2020-04-01 |
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